The present invention relates to a semiconductor memory being provided with refresh circuity and to improvements in a semiconductor memory for storing a moving picture or a static picture, in a moving-picture storing memory, in a moving-picture storing apparatus, in a moving-picture displaying apparatus, in a static-picture storing memory, and in an electronic notebook.
in a dynamic RAM (hereinafter referred to as DRAM) which permits the highest integration of all the semiconductor memories, a memory cell serving as a unit for storing information consists of a single transistor and a single capacitor, so that information is stored by charging the above capacitor. However, since tile charge stored on the capacitor leaks off due to its structure, the DRAM requires the refresh operation of periodically recharging the capacitor.
The refresh operation is performed by the following procedures: a word line serving as the gate of the transistor in a memory cell is selected; infinitesimal signals are transferred from all the capacitors connected to the selected word line to bit lines, which are equal in number to the capacitors, and amplified by means of sense amplifiers, which are equal in number to the bit lines; and the capacitors in all the memory cells are recharged. Since a single cycle of operation is complete on a word-line basis, all the word lines are selected periodically so as to activate the sense amplifiers. In general, a refresh operation is performed by interrupting a normal read/write operation. The interruption of the normal operation consequently disables an access to the memory itself, which bringing the system itself into the standby state, so that the operating efficiency of the system is lowered. Moreover, since tile system also executes a command to perform the refresh operation, additional circuits in the system are increased in number, resulting in complicated control.
In the development of DRAMs to which the refresh operation for their memory cells is dispensable as described above, larger capacity as well as higher performance have been pursued in recent years. As for the former pursuit of larger capacity, higher integration has been achieved at the rate of quadrupling the storage capacity of an existing DRAM every three years. With the leading-edge technology, a DRAM having a capacity as large as 256M bits per chip is under development. The latter pursuit of higher performance has been accomplished by implementing a higher-speed and lower-power operation. As for the higher-speed operation, for example, it has been implemented in such a manner that data is inputted and outputted sequentially in synchronization with an external clock by specifying only the leading address (hereinafter referred to as serial access), not in a conventional manner which assumes completely random addressing. A frequency as high as about 100 MHz has been required as the frequency of a clock, while a DRAM which satisfies the above requirement has been appearing on the market. On the other hand, the application of DRAMs which enables a serial high-speed access to data, not random, has been in great demand in the field of image-related devices.
As an image memory for use in these image-related devices, a field memory has conventionally been manufactured for a is commercial purpose. The leading-edge field memory, which has a capacity of 4M bits per chip, operates at a frequency of 50 to 100 MHz. Since all the word lines are sequentially selected in the image memory, it follows that a refresh operation is performed equivalently. In the case of operating a 4M bit DRAM of 8-bit parallel type at 50 MHz, only 10 milliseconds is substantially required to read out the whole 4M bits, though the spec of the refresh cycle is 16 milliseconds, so that it will be appreciated that the refresh operation is not necessary.
Although it is highly predictable that a chip having a capacity of 256M bits and operating at 100 MHz will be in future demand for storing images or the like, if the whole 256M bits are to be read out with an input/output unit of 16-bit parallel type, for example, an operation at 100 MHz requires about 168 milliseconds. Since DRAMs require periodical refreshing, as described above, and the supposed spec of the refresh cycle for the 256M-bit DRAM is about 128 milliseconds, it is necessary to perform a refresh operation by interrupting a serial-access operation, which may interfere with tile high-speed operation of the system with faster cycle time.
The foregoing statement is summarized in the following table which shows the capacities, refresh periods, and time required to access all the bits of DRAMs in individual generations. Since the data transfer rate for high-definition television (HDTV) is 1. 2 G bits/second, it is assumed that the operating frequency of each DRAM is 80 MHz and its input/output unit is of 16-bit parallel type.
TABLE 1 ______________________________________ REFRESH TIME REQUIRED FOR CAPACITY PERIOD FULL-BIT ACCESS ______________________________________ 1 M 8 ms 0.82 ms 4 M 16 ms 3.28 ms 16 M 32 ms 13.1 ms 64 M 64 ms 52.4 ms 256 M 128 ms 209.7 ms ______________________________________
As can be seen from the foregoing table, if all the bits in a serial memory having a capacity on the order of 1M to 64M bits are sequentially accessed, it means that a refresh operation is performed equivalently. With a memory having a larger capacity on the order of 256M bits, however, the refresh operation is required even in a serial access memory as well as in a random access memory, so that the operating efficiency of the system is lowered due to the refresh operation.
To overcome the above problem, there has conventionally been used a virtual SRAM ( see, for example, 1987 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.20-21, February 1987 or Nikkei Electronics, pp.167-184, Apr. 6, 1987). The virtual SRAM is constituted so that a refresh signal is generated therein in order to perform a refresh operation, while the normal operation is brought into the standby state. That is, although the refresh operation is not seemingly performed in the virtual SRAM when viewed from the outside, a refresh operation is performed automatically under the internal control of the virtual SRAM (hereinafter referred to as self-refresh). If a normal access from the outside competes with a self-refresh access, the refresh access is preferentially enabled, while the normal access is brought into the standby state, as shown in the timing chart of FIG. 14(a). Initially, a word line is activated so as to perform a self-refresh operation, followed by the selection of another word line in accordance with a normal-access enable signal/CE and with an external address, so that data is read out and appears at an input/output port I/O. However, since the above conventional virtual SRAM is constituted so that the normal access is enabled after the refresh access was preferentially enabled, the access time for a word line is disadvantageously increased (hereinafter referred to as word-line delay). As a result, if the refresh access competes with the normal access, the time elapsed till the read-out data appears is increased, as shown in FIGS. 14(a) and 14(b), so that the cycle time of the virtual SRAM is disadvantageously increased because the minimum cycle time of the virtual SRAM is equal to the sum of the cycle time of the normal access and the cycle time of the self-refresh.
Below, a specific description will be given to adverse effects caused by the word-line delay. Since it is often the case with a serial access memory that a single chip is operated both at a high frequency and at a low frequency, the description will be given to the case where the operation is alternately performed at, e.g., higher-rate 100 MHz and at lower-rate 10 MHz. Since the access time for a DRAM (including time required to access a word line) is about 60 ns, data is outputted 6 clocks after the initiation of the access to the memory in the case of operating at 100 MHz. With the virtual SRAM, however, the amount of word-line delay is generally about 30 ns, so that the access time is increased by about 30 ns for the word-line delay, thus outputting data 9 clocks after the initiation of the access in the case of operating at 10 MHz, on the other hand, since it is necessary to use the same clock timing as used in the case of operating at 100 MHz described above, it becomes necessary to output data in 600 ns (=100 ns.times.6 clocks) without the word-line delay and in 900 ns (=100 ns.times.9 clocks) with the word-line delay. Consequently, if the amount of word-line delay is large, it becomes necessary to provide an additional circuit for delaying data inside the chip as well as an additional circuit for delaying the timing of fetching data outside the chip, each of which is not required there is no word-line delay. Although the amount of delay in the case of operating at 100 MHz is 3 clocks in the above description, it reaches 15 clocks in the case of operating at 500 MHz, so that the above problem becomes more conspicuous as the operating frequency becomes higher.
Meanwhile, a large-capacity DRAM has been regarded as a promising semiconductor memory for storing a moving picture, since the moving picture entails an extremely large amount of data and a high data transfer rate.
In view of the foregoing, a DRAM exclusively for storing images with a capacity of about 256K bits has conventionally been developed in order to process a digital signal. Such a DRAM is introduced in, for example, Ishimoto et al., "A Screen Size Serial Access Memory for Video Applications," 10th European Solid-State Circuits Conference, pp.149-152, (September 1984) and in Kotani et al., "A 50 MHz 8 Mb Video RAM with a Column Direction Drive Sense Amplifier," 1989 Symposium on VLSI circuits, 8-4, pp.105-106, (May 1989).
FIG. 27 is a schematic view of a conventional semiconductor memory, in which a reference numeral 215 designates a system clock, 216 designates a write control signal, 290 designates a data input/output unit for receiving external data or outputting internal data to the outside in accordance with the system clock 215 and with the write control signal mentioned above, and 296 designates a memory cell array which is connected to the above data input/output unit 290 via a data register 295. The data register 295 performs serial-to-parallel conversion or parallel-to-serial conversion with respect to data.
A reference numeral 292 designates an external address bus, 297 designates a/CAS signal, 298 designates a/RAS signal, and 294 designates an address input unit for receiving an external address from the above external address bus 292. Inside the address input unit are provided a column-address input element 299 and a row-address input element 291. The above column-address input element 299 predecodes the inputted external address in accordance with the system clock 216 and with the /CAS signal 297. The row-address input element 291 predecodes the inputted external address in accordance with the /RAS signal 298 and outputs the predecoded address to the memory cell array 296 via the internal address bus 293.
The data in the data input/output unit 290 is converted to parallel data by the data register 295 and then inputted to the memory cell array 296. On the other hand, the data on the external address bus 292 is inputted to the address input unit 294 and predecoded by the row-address input element 291 and column-address input element 299 inside the address input unit 294, so as to be transmitted to the memory array 296 via the internal address bus 293. The memory cell array 296 stores the above inputted data at one address after another in the order in which it is selected by the above address bus 293.
However, since each of the above conventional semiconductor memory chips is small in capacity, it can store data only on a static picture (1 field, 1 frame). Consequently, with a simple combination of the chip structure and large capacity, only a static picture (1 field, 1 frame) with an extremely large amount of data can be stored. Although a moving picture can be considered as a sequence or static pictures, since the conventional technology does not permit a distinction between moving pictures and static pictures, it is difficult to constitute a DRAM for storing moving and static pictures, which are often treated in images.
To eliminate the above disadvantage, there can be considered the provision of a storing means for counting the number of inputted row addresses till it reaches a specified value sufficient to form one image and storing the row address at the time when the number of inputted row addresses reached the specified value. However, such a structure is intricate and is substantially incompatible with a moving picture or static picture entailing a large number of images.